In this proposed project, we focus on scaling up the performance of P4-based programmable data plane functions using DPDK and VPP. We assume an environment where network functions and chained network services are implemented in P4 language and executed on a multicore x86 platform. Specifically, we are motivated to achieve the following objectives: 1) P4 data plane acceleration with VPP: accelerate the P4 based packet processing with the VPP capability on a multi-core x86 system. We plan to design a software tool to automatically map a P4 program to VPP-based packet processing framework, and create a new VPP-based P4 behavior model that takes advantage of the packet level parallelism; 2) Compare VPP with DPDK: compare the performance of VPP accelerated P4 network functions with the corresponding DPDK pipeline version that is pursued in prior arts. In addition, we will apply Intel Profile-guided Optimization technique to detect and provide opportunities to optimize the performance of the system; 3) System and architecture level performance analysis: evaluate the impact of VPP accelerated P4 network functions from both micro-architecture and system levels by using Linux and Intel VTune toolsets. This work will lead to insights of the impact of the architecture factors on performance of multicore- based software data plane.
April 2017 – present